Non-volatile memory (NVM) arrays, such as erasable, programmable read only memory (EPROM) or flash memory arrays, or electrically erasable, programmable read only memory (EEPROM) arrays, require high positive or negative voltages to program and erase memory cells of the array. NVM cells generally comprise transistors With programmable threshold voltages. For example, one type of non-volatile cell is a nitride, read only memory (NROM) cell, described in U.S. Pat. No. 6,011,725.
One procedure for programming bits, for example, in NROM cells, is by the application of programming pulses to Word lines and bit lines so as to increase the threshold voltage of the bits to be programmed. After application of one or more sets of programming pulses, the threshold voltages of the bits that are to be programmed may be verified to check if the threshold voltages have been increased to a target programmed state. Any bit that fails the program verify operation may undergo one or more additional programming pulses. The sequence of application of programming pulses followed by verification may then continue until all the bits that should be programmed have reached the target programmed state.
Read and write operations may be carried out using voltages that are regulated to be above a positive voltage supply Vdd. The circuitry that supplies and controls the programming and verification voltages may include a high voltage driver or high voltage pump.
Reference is made to FIG. 1, which illustrates a simplified block diagram of a voltage driver 10 with a model of output node. The voltage driver of FIG. 1 may include a line for input signal IN, a high voltage source HV that may be used as the source to drive the voltage, and an output line OUT that may carry the voltage from driver 10 to load 20. Output node nOUT may be charged by high voltage source HV through a PMOS (p-channel metal oxide semiconductor) transistor P0 and may be discharged to ground through an NMOS (n-channel metal oxide semiconductor) transistor N0. The drain of P0 may be connected via nOUT to the source of N0. However, the efficiency of a conventional voltage driver, such as the one shown in FIG. 1, is relatively low, reaching as low as 40%.
One solution to conserve high voltage power is to precharge the output node nOUT using a low voltage source prior to charging it using a high voltage source. Reference is made to FIG. 2, which illustrates a simplified block diagram of a high voltage driver 30 with Vcc pre charge. Components of the circuitry of FIG. 2 that are similar to that of FIG. 1 are designated with the same reference labels, and for the sake of brevity the description is not repeated. In the described high voltage driver 30 with Vcc precharge, a first high voltage input IN1-P may control PMOS transistor P0 and input IN1-N may control NMOS transistor N0 to charge high voltage, and a second high voltage input IN2 may precharge output node nOUT to Vcc.
However, the above high voltage driver with Vcc precharge needs additional high voltage circuitry for generation of a second high voltage input signal IN2, and current protection between Vcc, HV, and ground during switching of PMOS transistor P0, and NMOS transistors N0 and N1.
For example, in order to open NMOS transistor N1, which is dedicated to precharge output node nOUT to Vcc, the voltage of input IN2 must be higher than Vcc plus the threshold voltage of N1. To reach the desired voltage level, an additional voltage source, for example, HV, and a high voltage level shifter for transformation of low voltage input signal IN2 to high voltage input signal IN1-N and IN1-P may be used.
An additional drawback of the described high voltage driver with Vcc precharge is the contention between HV and VCC. Input signal IN1 in FIG. 2 is separated to two input signals, IN1-P which is applied to the gate of PMOS transistor P0 and IN1-N which is applied to the gate of NMOS transistor N0. However, this configuration raises practical difficulties in implementation. For example, before the high voltage phase, NMOS transistor N1 has to be closed and only after it is closed PMOS transistor P0 can be open. In any other configuration VCC and HV source will be shorted. Thus, the control of the switch between NMOS transistor N1 and PMOS transistor P0, without overlapping raises an additional difficulty. The non-overlapping signals for NMOS transistor N1 and PMOS transistor P0 influence also on the time required for the switching. Therefore, this kind of driver can not be used for fast switching schemes.
In addition, practical realization on of the described driver may be complicated in respect of the required silicon area, high voltage power consumed and loss of power for switching additional control signals. In addition, the described driver may suffer from other disadvantages.
Accordingly, there is a need for an efficient high voltage driver.